00734nam a2200253 i 4500 19918506 BD-KhUET 20251218102944.0 251218s2018 flu 001 0 eng 2017022734 9780367778811 DLC eng rda DLC BD-KhUET 621.381 23 Cavanagh, Joseph, Verilog HDL design examples / Joseph Cavanagh. London : CRC Press, c2018. xv, 655 p. : ill. ; 26 cm Includes index. Digital electronics Computer-aided design. Logic design. Verilog (Computer hardware description language) ddc BK 19008 19008 0 0 ddc 0 1 KUETCL KUETCL DISPLAY 2025-07-09 Purchased through EIAA Project (DPM) 6486.16 0 621.381 CAV 3010063729 2025-12-18 10:32:02 01 2025-12-18 BK ECE